In recent years, with semiconductor devices formed by packaging, downsizing and densification of packages themselves accompanying downsizing and enhanced functionality of electronic devices have led to demands for an increase in the number of terminals in the semiconductor devices. Accordingly, various chip scale packages (CSPs) are being developed as downsized packages having a large number of terminals.
In particular, a wafer level CSP (WLCSP) is recently attracting attention as a technique capable of realizing an ultimate miniature package equivalent to a bare chip. The WLCSP is formed by first forming an insulating resin film on the entire surface of a semiconductor wafer on which a plurality of integrated circuits is formed, next forming wiring that electrically connects pad electrodes of the integrated circuits with external terminals such as bumps via contact holes on the formed insulating resin film, and in a final step, splitting the semiconductor wafer into chips.
In addition, a semiconductor package has been released in which an inductor element, conventionally a so-called external part separate from a semiconductor chip, is formed on an insulating resin film in a WLCSP-type semiconductor device using material for wiring to external terminals. The WLCSP-type semiconductor device including an inductor element is also expected as a microminiature semiconductor package applicable to applications ranging from several hundred MHz to several GHz such as mobile devices, wireless LAN apparatuses, and the like.
A conventional semiconductor device will now be described in detail with reference to FIGS. 10, 11, 12 and 13.
FIG. 10 is a cross-sectional diagram of substantial parts of the configuration of a conventional semiconductor device and a corresponding wiring layout diagram; FIG. 11 is a diagram showing a mounted state of a conventional WLCSP; FIG. 12 is an enlarged view of substantial parts showing the mounted state of the conventional WLCSP; and FIG. 13 is a diagram showing a load applied in the vicinity of semiconductor wiring and a stress concentration site during mounting of the conventional WLCSP.
In addition, FIG. 12 is an enlarged view of section A shown in FIG. 11, and FIG. 13 is an enlarged view of section B shown in FIG. 12.
In FIGS. 10, 11, 12 and 13, reference numeral 1 denotes a molding resin, 2 a post, 3 rewiring, 4 a solder bump, 5 an insulating film, 6 an Al wiring pad, 7 an Al wiring inductor, 8 first signal wiring, 9 second signal wiring, 10 a surface protective film, 11 an interlayer insulating film, 12 a semiconductor substrate, 13 a mounting substrate, 14 a mounting substrate terminal, 17 a crack, 18 a WLCSP, and 19 a stress concentration site.
First, the configuration of a conventional semiconductor device will be described with reference to FIG. 10. As shown in FIG. 10, in a semiconductor device, for example, a semiconductor element such as an MOS transistor and a semiconductor element such as a diode, a bipolar transistor, or the like formed by a PN junction are formed on the semiconductor substrate 12. The semiconductor substrate 12 is covered by the interlayer insulating film 11 to protect the semiconductor elements. Also disposed on the semiconductor substrate 12 are; the first signal wiring 8 for conducting a signal from the semiconductor element; the second signal wiring 9 provided on the first signal wiring 8 and which is electrically insulated by the interlayer insulating film 11 using a multilayer wiring technique; the Al wiring inductor 7; and the Al wiring pad 6 for extracting signals to the outside. Such components are electrically or atmospherically insulated from the outside and protected by the surface protective film 10.
Next, wiring is disposed to under the solder bump 4 using the rewiring 3 in order to actually extract a signal from the Al wiring pad 6 to the outside. The solder bump 4 and the rewiring 3 are connected via the post 2 for increased mounting reliability. The post 2 and the rewiring 3 are protected from external impact and the atmosphere by the molding resin 1. In addition, the solder bump 4 to become a contact that connects to the mounting substrate is formed on the post 2. In consideration of inductor characteristics, wiring having a thick film thickness of around 2 μm is used for the second signal wiring 9, the Al wiring pad 6 and the Al wiring inductor 7. In comparison, the surface protective film 10 is thinly formed with respect to the second signal wiring 9.
Furthermore, the second signal wiring 9 is disposed directly beneath an outer peripheral portion of the post 2 as indicated in the section B in FIG. 12 at an outermost peripheral terminal of the WLCSP 18 as indicated in the section A in FIG. 11.
In FIG. 11, the WLCSP 18 is formed on the mounting substrate 13 with a face including the solder bumps 4 facing downwards, and is placed on the mounting substrate terminals 14. Subsequently, a heat treatment process (220 to 260 degrees C.) is performed and the solder bumps 4 are melted and joined with the mounting substrate terminals 14 (for example, refer to Patent Document 1).
FIG. 13 is a diagram of the WLCSP 18, in which the solder bumps 4 are disposed, showing load application states of peripheral members and the stress concentration site 19 during the heat treatment process with respect to the solder bumps 4 disposed at the outermost peripheral portion of the WLCSP 18 as well as the second signal wiring 9 and the surface protective film 10 disposed under the post 2.